Features and Improvements
- Transient Stability: Added error checking for WT3G2, WT3G, WT4G, WT4G1 and REGC_A so that if LVPL=0 then it ignores the low voltage power logic
- Transient Stability: For LD1PAC, when fuvr=0 we were still reporting transient stability events related to the pickup of the under voltage relay even though it would never actually open anything. This has been fixed to no longer report these events if fuvr=0.
- Transient Stability: fixed errors in using a CIM6 motor model which resulted in an access violation
- Transient Stability: When reading a DYD file, netting records which had a line of text listing only ONE bus listed were not being properly read (2 or more worked fine). This has been fixed to properly read the buses and disable stability models.
- Transient Stability: For generator transient stability models of SVCs, any MW output of the generator was not properly accounted for in transient stability. This has been fixed.
- Transient Stability: Added a fix for the previous patch which ignored CMPLDW models which were negative.
- Transient Stability: modified SVCWSC and VWSCC to ignore the fast override block if DV=0.
- Transient Stability: Fixed error in current control of the CONV_Adelanto and CONV_IntMtnPP multi-terminal DC line transient stability model.